In some applications, DC/DC converters may be operated using high switching frequencies. For example, in order to meet response time requirements for particular loads, switching frequencies on the order of tens to hundreds of megahertz may be needed. However, with higher switching frequencies, the power dissipated as a result of the gate switching loss may increase to an unacceptable level.
FIG. 1 shows a DC/DC converter system 100 in a step-down configuration known as a “buck” configuration. A pulse width modulator (PWM) controller 110 controls a p-switch 120 and an n-switch 130, which are implemented using power transistors. A load 140 may be coupled with the output of p-switch 120 and n-switch 130 via an inductor 150 and a capacitor 160.
System 100 may dissipate power in a number of ways, each of which decreases the efficiency of the system. For example, resistive losses due to the on-state drain/source resistance (referred to as Rds-on) reduce the efficiency of the system. In order to reduce power loss due to Rds-on, larger transistors may be used.
However, larger transistors exhibit increased capacitance between the gate and the source, Cgs. This in turn increases what is termed the gate loss of the transistor. For a voltage V being switched at a frequency f across a capacitance Cgs, the gate loss is given by Equation (1) below:Gate loss=½CgsV2f  Equation (1)
At relatively low frequencies (for example, frequencies on the order of about 100 kHz), the gate loss may be significantly less than Rds-on. However, as higher switching frequencies are used, gate loss may make a substantial contribution to the power dissipation in system 100.